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UID:submissions.supercomputing.org_SC21_sess343_misc398@linklings.com
SUMMARY:Hardware Specialization for Efficiency and Performance
DESCRIPTION:Workshop\n\nHardware Specialization for Efficiency and Perform
 ance\n\nChiou\n\nWith the demise of Dennard scaling and the slowing of Moo
 re’s Law, hardware specialization is one of very few ways to improve energ
 y efficiency and/or performance. The standard way to specialize is to add 
 dedicated accelerators implemented as on-die fixed function circuits that 
 are orders of magnitude more computationally efficient than standard proce
 ssors. Those accelerators could be connected to the rest of the system thr
 ough a network-on-chip or integrated into an application specific processo
 r (ASP) that has further data path and/or memory system optimizations.  Su
 ch approaches are often referred to as Application-Specific Integrated Cir
 cuits (ASIC).  \n\nIn this talk, I will discuss an alternative hardware s
 pecialization based on reconfigurable logic as is found in field programma
 ble gate arrays (FPGAs).  Conventional wisdom says that FPGAs are an order
  of magnitude less power efficient, an order of magnitude less performant,
  and an order of magnitude larger than ASICs, as well as being harder to p
 rogram.  When analyzed in a full system context, however, FPGAs are signif
 icantly better than the conventional wisdom and, in some cases, are more e
 fficient than ASIC alternatives.  When combined with their other advantage
 s such as dynamic reconfigurability and wide applicability, FPGAs are far 
 more compelling than previously thought, even at cloud-scale volumes. I wi
 ll describe why the conventional wisdom should be reexamined, give example
 s of novel uses and cloud deployments of FPGAs, and describe how FPGAs cou
 ld be made easier to program.\n\nTag: Accelerator-based Architectures, App
 lications, Architectures, Emerging Technologies, Heterogeneous Systems, Me
 mory Systems, Networks\n\nRegistration Category: Workshop Reg Pass
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