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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211207T055402Z
LOCATION:231-232
DTSTART;TZID=America/Chicago:20211115T113000
DTEND;TZID=America/Chicago:20211115T120000
UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc101@linklings.com
SUMMARY:Efficient HW and SW Interface Design for Convolutional Neural Netw
 orks Using High-Level Synthesis and TensorFlow
DESCRIPTION:Workshop\n\nEfficient HW and SW Interface Design for Convoluti
 onal Neural Networks Using High-Level Synthesis and TensorFlow\n\nMishra, 
 kindratenko\n\nHardware accelerators have been extensively used for the de
 ployment of convolutional neural networks (CNNs) as they offer speedup by 
 extracting the parallelism existing in CNNs. The development of such accel
 erators spans a large design space. The figures of merit of an accelerator
  are its frequency of operation, the number of operations performed per un
 it time, and supported configurations and thus it makes the design a multi
 -objective optimization problem. This work presents a systematic approach 
 to develop an efficient framework for CNN that qualifies such merits and c
 an be scaled to different configurations using Xilinx Vitis-HLS. The prese
 nted framework utilizes four copies of a single unified module for executi
 ng convolution and pooling in hardware and uses TensorFlow to run certain 
 layers in software using multiprocessing. The framework has been evaluated
  with Squeezenet1.0, VGG16, and Resent50 at 250 MHz clock frequency on the
  Xilinx Alveo U250 board achieving 750 GOPS.\n\nTag: Accelerator-based Arc
 hitectures, Applications, Architectures, Emerging Technologies, Heterogene
 ous Systems, Memory Systems, Networks\n\nRegistration Category: Workshop R
 eg Pass
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