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DTSTAMP:20211207T055402Z
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DTSTART;TZID=America/Chicago:20211115T163000
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UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc103@linklings.com
SUMMARY:Portable Compilation of NumPy to FPGAs
DESCRIPTION:Workshop\n\nPortable Compilation of NumPy to FPGAs\n\nde Fine 
 Licht, De Matteis, Ziogas, Ben-Nun, Hoefler\n\nWhile the reconfigurable ha
 rdware community has transitioned from RTL to C-based languages, the HPC c
 ommunity is moving on to Python as the language of choice for application 
 development. We show how the Data-Centric Parallel Programming (DaCe) fram
 ework is a powerful tool to pursue this trend for FPGA development, allowi
 ng NumPy-based Python programs to be compiled to both Xilinx and Intel FPG
 As through a data movement-oriented intermediate representation with no ch
 anges to the original program, providing a high quality baseline amenable 
 to further optimization. We present results for all 30 kernels from the Po
 lyBench benchmark suite for both FPGA vendors compiled from the same Pytho
 n code, preserving high-level semantics to embed specialized hardware impl
 ementations in the code-generated architectures.\n\nTag: Accelerator-based
  Architectures, Applications, Architectures, Emerging Technologies, Hetero
 geneous Systems, Memory Systems, Networks\n\nRegistration Category: Worksh
 op Reg Pass
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