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DTSTART;TZID=America/Chicago:20211115T120000
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UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc104@linklings.com
SUMMARY:Optimizing a Hardware Network Stack to Realize an In-Network ML In
 ference Application
DESCRIPTION:Workshop\n\nOptimizing a Hardware Network Stack to Realize an 
 In-Network ML Inference Application\n\nHartmann, Weber, Wirth, Sommer, Koc
 h\n\nFPGAs are an interesting platform for the implementation of network-a
 ttached accelerators, either in the form of smart network interface cards 
 or as In-Network Processing accelerators.\n\nBoth application scenarios re
 quire a high-throughput hardware network stack. In this work, we integrate
  such a stack into the open-source TaPaSCo framework and implement a libra
 ry of easy-to-use design primitives for network functionality in modern HD
 Ls. To further facilitate the development of network-attached FPGA acceler
 ators, the library is complemented by a handy simulation framework. \n\nIn
  our evaluation, we demonstrate that the integrated and extended stack can
  operate at or close to the theoretical maximum, both for the stack itself
  as well as an network-attached machine learning inference appliance.\n\nT
 ag: Accelerator-based Architectures, Applications, Architectures, Emerging
  Technologies, Heterogeneous Systems, Memory Systems, Networks\n\nRegistra
 tion Category: Workshop Reg Pass
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