BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20211207T055402Z
LOCATION:231-232
DTSTART;TZID=America/Chicago:20211115T161500
DTEND;TZID=America/Chicago:20211115T163000
UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc105@linklings.com
SUMMARY:Device_global: A SYCL Extension Introducing Device-Scoped Allocati
 ons to Enhance Performance and Usability
DESCRIPTION:Workshop\n\nDevice_global: A SYCL Extension Introducing Device
 -Scoped Allocations to Enhance Performance and Usability\n\nKinsner, Radzi
 khovskyy, Garvey\n\nField programmable gate arrays (FPGAs) are increasingl
 y targeted by high level programming languages including C++, OpenCL, SYCL
 , and DPC++. Device-side language constructs are often designed first to t
 arget graphics processing units (GPUs) due to their proliferation, so ther
 e are design gaps to fill when enhancing languages to target reconfigurabl
 e architectures.  One key gap in the SYCL specification is the ability to 
 declare memory shared between kernels or functions on a single device, whi
 ch can be implemented using efficient on-chip reconfigurable memory resour
 ces of an FPGA.\n\nThis talk will describe a new language extension for DP
 C++ that will subsequently be proposed for the next SYCL specification, an
 d which enables device-scope memory allocations that are accessed like the
 y are global variables.  This feature is important for spatial architectur
 es in two ways: (1) it enables construction and additional optimization us
 ing on-chip memory resources; and (2) allows semantics to be defined aroun
 d reprogramming and initialization of data in an efficient way for reconfi
 gurable architectures.\n\nThe talk will detail the semantics and optimizat
 ion opportunities enabled by the extension, aspects of lifetime and initia
 lization, controls enabling optimization on FPGA (both hints and semantic 
 modifiers), and divergence from the existing OpenCL/SPIR-V program/module 
 scope variable features.  These benefits combine to close a recurring gap 
 in the device language across architectures.  The device_global feature en
 ables both performance and usability in common coding patterns, and is the
  result of significant work that aims to inform the next version of the SY
 CL specification.\n\nTag: Accelerator-based Architectures, Applications, A
 rchitectures, Emerging Technologies, Heterogeneous Systems, Memory Systems
 , Networks\n\nRegistration Category: Workshop Reg Pass
END:VEVENT
END:VCALENDAR