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UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc107@linklings.com
SUMMARY:Porting In-Compressible Flow Matrix Assembly to FPGAs for Accelera
 ting HPC Engineering Simulations
DESCRIPTION:Workshop\n\nPorting In-Compressible Flow Matrix Assembly to FP
 GAs for Accelerating HPC Engineering Simulations\n\nBrown\n\nEngineering i
 s an important domain for supercomputing, with the Alya model being a popu
 lar code for undertaking such simulations. With ever increasing demand fro
 m users to model larger, more complex systems at reduced time to solution 
 it is important to explore the role that novel hardware technologies, such
  as FPGAs, can play in accelerating these workloads on future exascale sys
 tems. \n\nIn this paper, we explore the porting of Alya's in-compressible 
 flow matrix assembly kernel, which accounts for a large proportion of the 
 model runtime, onto FPGAs. After describing in detail successful strategie
 s for optimisation at the kernel level, we then explore sharing the worklo
 ad between the FPGA and host CPU, mapping most appropriate parts of the ke
 rnel between these technologies, enabling us to more effectively exploit t
 he FPGA. We then compare the performance of our approach on a Xilinx Alveo
  U280 against a 24-core Xeon Platinum CPU and Nvidia V100 GPU, with the FP
 GA significantly out-performing the CPU and performing comparably against 
 the GPU, whilst drawing substantially less power. The result of this work 
 is both an experience report describing appropriate dataflow optimisations
  which we believe can be applied more widely across HPC codes, and a perfo
 rmance comparison for this specific workload that demonstrates the potenti
 al for FPGAs in accelerating HPC engineering simulations.\n\nTag: Accelera
 tor-based Architectures, Applications, Architectures, Emerging Technologie
 s, Heterogeneous Systems, Memory Systems, Networks\n\nRegistration Categor
 y: Workshop Reg Pass
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