BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Chicago
X-LIC-LOCATION:America/Chicago
BEGIN:DAYLIGHT
TZOFFSETFROM:-0600
TZOFFSETTO:-0500
TZNAME:CDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0500
TZOFFSETTO:-0600
TZNAME:CST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20211207T055402Z
LOCATION:231-232
DTSTART;TZID=America/Chicago:20211115T154500
DTEND;TZID=America/Chicago:20211115T161500
UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc111@linklings.com
SUMMARY:Enhancing the Scalability of Multi-FPGA Stencil Computations via H
 ighly Optimized HDL Components
DESCRIPTION:Workshop\n\nEnhancing the Scalability of Multi-FPGA Stencil Co
 mputations via Highly Optimized HDL Components\n\nDel Sozzo\n\nStencil-bas
 ed algorithms are a relevant class of computational kernels in high-perfor
 mance systems, as they\nappear in a plethora of fields, from image process
 ing to seismic simulations, from numerical methods to physical modeling. A
 mong the various incarnations of stencil-based computations, Iterative Ste
 ncil Loops (ISLs)\nand Convolutional Neural Networks (CNNs) represent two 
 well-known examples of kernels belonging\nto the stencil class. Indeed, IS
 Ls apply the same stencil several times until convergence, while CNN layer
 s\nleverage stencils to extract features from an image. The computationall
 y intensive essence of ISLs, CNNs, and\nin general stencil-based workloads
 , requires solutions able to produce efficient implementations in terms of
 \nthroughput and power efficiency. In this context, FPGAs are ideal candid
 ates for such workloads, as they allow\ndesign architectures tailored to t
 he stencil regular computational pattern. Moreover, the ever-growing need\
 nfor performance enhancement leads FPGA-based architectures to scale to mu
 ltiple devices to benefit from\na distributed acceleration. For this reaso
 n, we propose a library of HDL components to effectively compute\nISLs and
  CNNs inference on FPGA, along with a scalable multi-FPGA architecture, ba
 sed on custom PCB interconnects. Our solution eases the design flow and gu
 arantees both scalability and performance competitive\nwith state-of-the-a
 rt works.\n\nTag: Accelerator-based Architectures, Applications, Architect
 ures, Emerging Technologies, Heterogeneous Systems, Memory Systems, Networ
 ks\n\nRegistration Category: Workshop Reg Pass
END:VEVENT
END:VCALENDAR
