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DTSTAMP:20211207T055402Z
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DTSTART;TZID=America/Chicago:20211115T143000
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UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc112@linklings.com
SUMMARY:A Framework for Customizable FPGA-based Image Registration Acceler
 ators
DESCRIPTION:Workshop\n\nA Framework for Customizable FPGA-based Image Regi
 stration Accelerators\n\nConficconi\n\nImage Registration is a highly comp
 ute-intensive optimization procedure that determines the geometric transfo
 rmation to align a\nfloating image to a reference one. Generally, the regi
 stration targets\nare images taken from different time instances, acquisit
 ion angles,\nand/or sensor types. Several methodologies are employed in th
 e\nliterature to address the limiting factors of this class of algorithms,
 \namong which hardware accelerators seem the most promising solution to bo
 ost performance. However, most hardware implementations are either closed-
 source or tailored to a specific context,\nlimiting their application to d
 ifferent fields. For these reasons, we\npropose an open-source hardware-so
 ftware framework to generate\na configurable architecture for the most com
 pute-intensive part of\nregistration algorithms, namely the similarity met
 ric computation.\nThis metric is the Mutual Information, a well-known calc
 ulus from\nthe Information Theory, used in several optimization procedures
 .\nThrough different design parameters configurations, we explore\nseveral
  design choices of our highly-customizable architecture and\nvalidate it o
 n multiple FPGAs. We evaluated various architectures\nagainst an optimized
  Matlab implementation on an Intel Xeon\nGold, reaching a speedup up to 2.
 86×, and remarkable performance\nand power efficiency against other state-
 of-the-art approaches.\n\nTag: Accelerator-based Architectures, Applicatio
 ns, Architectures, Emerging Technologies, Heterogeneous Systems, Memory Sy
 stems, Networks\n\nRegistration Category: Workshop Reg Pass
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