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DTSTAMP:20211207T055402Z
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DTSTART;TZID=America/Chicago:20211115T140000
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UID:submissions.supercomputing.org_SC21_sess343_ws_h2rc113@linklings.com
SUMMARY:Optimized Implementation of the HPCG Benchmark on Reconfigurable H
 ardware
DESCRIPTION:Workshop\n\nOptimized Implementation of the HPCG Benchmark on 
 Reconfigurable Hardware\n\nZeni\n\nThe HPCG benchmark represents a modern 
 complement to the HPL benchmark in the performance evaluation of HPC syste
 ms, as it has been recognized as a more representative benchmark to reflec
 t real-world applications. While typical workloads become more and more ch
 allenging, the semiconductor industry is battling with performance scaling
  and power efficiency on next-generation technology nodes. As a result, th
 e industry is turning towards more customized compute architectures to hel
 p meet the latest performance requirements. In this paper, we present the 
 details of the first FPGA-based implementation of HPCG that takes advantag
 e of such customized compute architectures. Our results show that our high
 -performance multi-FPGA implementation, using 1 and 4 Xilinx Alveo U280 ac
 hieves up to 108.3 GFlops and 346.5 GFlops respectively, representing spee
 d-ups of   104.1×  and   333.2×  over software running on a server with an
  Intel Xeon processor with no loss of accuracy. We also demonstrate that t
 he FPGA-based solution achieves comparable performance with respect to mod
 ern GPUs and an up to   2.7×  improvement in terms of power efficiency com
 pared to an NVIDIA Tesla V100. Finally, a theoretical evaluation, based on
  Berkeley’s Roofline model demonstrates that our implementation is near op
 timally tuned on the Xilinx Alveo U280.\n\nTag: Accelerator-based Architec
 tures, Applications, Architectures, Emerging Technologies, Heterogeneous S
 ystems, Memory Systems, Networks\n\nRegistration Category: Workshop Reg Pa
 ss
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