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DTSTAMP:20211207T055402Z
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DTSTART;TZID=America/Chicago:20211115T090000
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UID:submissions.supercomputing.org_SC21_sess343@linklings.com
SUMMARY:H2RC: Seventh International Workshop on Heterogeneous High-Perform
 ance Reconfigurable Computing
DESCRIPTION:Workshop\n\nA Framework for Customizable FPGA-based Image Regi
 stration Accelerators\n\nConficconi\n\nImage Registration is a highly comp
 ute-intensive optimization procedure that determines the geometric transfo
 rmation to align a\nfloating image to a reference one. Generally, the regi
 stration targets\nare images taken from different time instances, acquisit
 ion angles,\nand/or sensor types. Several meth...\n\n---------------------
 \nHardware Specialization for Efficiency and Performance\n\nChiou\n\nWith 
 the demise of Dennard scaling and the slowing of Moore’s Law, hardware spe
 cialization is one of very few ways to improve energy efficiency and/or pe
 rformance. The standard way to specialize is to add dedicated accelerators
  implemented as on-die fixed function circuits that are orders of magnitu.
 ..\n\n---------------------\nH2RC:  Lunch Break (12:30-2)\n\n\n\n---------
 ------------\nOptimized Implementation of the HPCG Benchmark on Reconfigur
 able Hardware\n\nZeni\n\nThe HPCG benchmark represents a modern complement
  to the HPL benchmark in the performance evaluation of HPC systems, as it 
 has been recognized as a more representative benchmark to reflect real-wor
 ld applications. While typical workloads become more and more challenging,
  the semiconductor industry i...\n\n---------------------\nPortable Compil
 ation of NumPy to FPGAs\n\nde Fine Licht, De Matteis, Ziogas, Ben-Nun, Hoe
 fler\n\nWhile the reconfigurable hardware community has transitioned from 
 RTL to C-based languages, the HPC community is moving on to Python as the 
 language of choice for application development. We show how the Data-Centr
 ic Parallel Programming (DaCe) framework is a powerful tool to pursue this
  trend for F...\n\n---------------------\nH2RC:  Afternoon Break (3-3:30)\
 n\n\n\n---------------------\nSeventh International Workshop on Heterogene
 ous High-Performance Reconfigurable Computing (H2RC)\n\nO'Brien, Bakos, Pl
 essl, Hoefler, Cappello\n\nAs conventional vonNeumann architectures are su
 ffering from rising power densities, we are facing an era with power, ener
 gy efficiency and cooling as first-class constraints for scalable HPC. FPG
 As can tailor the hardware to the application, avoiding overheads and achi
 eving higher hardware efficienc...\n\n---------------------\nEfficient HW 
 and SW Interface Design for Convolutional Neural Networks Using High-Level
  Synthesis and TensorFlow\n\nMishra, kindratenko\n\nHardware accelerators 
 have been extensively used for the deployment of convolutional neural netw
 orks (CNNs) as they offer speedup by extracting the parallelism existing i
 n CNNs. The development of such accelerators spans a large design space. T
 he figures of merit of an accelerator are its frequency ...\n\n-----------
 ----------\nNear-Data FPGA-Accelerated Processing of Collective and Infere
 nce Operations in Disaggregated Memory Systems\n\nHeinz, Koch\n\nWith grow
 ing data set sizes, many scientific and data center HPC workloads observe 
 an increasing scaling imbalance, e.g., between compute and memory capaciti
 es. As a solution, disaggregated system architectures employ spatial distr
 ibution of the different resources. They aim for independent scaling ...\n
 \n---------------------\nDevice_global: A SYCL Extension Introducing Devic
 e-Scoped Allocations to Enhance Performance and Usability\n\nKinsner, Radz
 ikhovskyy, Garvey\n\nField programmable gate arrays (FPGAs) are increasing
 ly targeted by high level programming languages including C++, OpenCL, SYC
 L, and DPC++. Device-side language constructs are often designed first to 
 target graphics processing units (GPUs) due to their proliferation, so the
 re are design gaps to fil...\n\n---------------------\nACCL: FPGA-Accelera
 ted Collectives over 100 Gbps TCP-IP\n\nHe, Parravicini, Petrica, O’Brien,
  Alonso...\n\nCollective operations such as scatter, gather, reduce, etc a
 re utilized broadly to implement distributed HPC applications and are the 
 target of extensive optimization in all MPI implementations as well as ded
 icated collective libraries by accelerator vendors (e.g. NCCL and RCCL by 
 NVidia and AMD res...\n\n---------------------\nH2RC 2021:  Opening Remark
 s\n\nBakos\n\n---------------------\nOptimizing a Hardware Network Stack t
 o Realize an In-Network ML Inference Application\n\nHartmann, Weber, Wirth
 , Sommer, Koch\n\nFPGAs are an interesting platform for the implementation
  of network-attached accelerators, either in the form of smart network int
 erface cards or as In-Network Processing accelerators.\n\nBoth application
  scenarios require a high-throughput hardware network stack. In this work,
  we integrate such a sta...\n\n---------------------\nThe Open Cloud Testb
 ed:  A Resource for FPGA and Cloud Researchers\n\nLeeser\n\n--------------
 -------\nEnhancing the Scalability of Multi-FPGA Stencil Computations via 
 Highly Optimized HDL Components\n\nDel Sozzo\n\nStencil-based algorithms a
 re a relevant class of computational kernels in high-performance systems, 
 as they\nappear in a plethora of fields, from image processing to seismic 
 simulations, from numerical methods to physical modeling. Among the variou
 s incarnations of stencil-based computations, Iterati...\n\n--------------
 -------\nH2RC:  Morning Break (10-10:30)\n\n\n\n---------------------\nPor
 ting In-Compressible Flow Matrix Assembly to FPGAs for Accelerating HPC En
 gineering Simulations\n\nBrown\n\nEngineering is an important domain for s
 upercomputing, with the Alya model being a popular code for undertaking su
 ch simulations. With ever increasing demand from users to model larger, mo
 re complex systems at reduced time to solution it is important to explore 
 the role that novel hardware technolog...\n\n\nTag: Accelerator-based Arch
 itectures, Applications, Architectures, Emerging Technologies, Heterogeneo
 us Systems, Memory Systems, Networks\n\nRegistration Category: Workshop Re
 g Pass
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