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DTSTAMP:20211207T055347Z
LOCATION:Online
DTSTART;TZID=America/Chicago:20211115T103000
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UID:submissions.supercomputing.org_SC21_sess422_ws_pmbsf104@linklings.com
SUMMARY:Multilevel Simulation-Based Co-Design of Next Generation HPC Micro
 processors
DESCRIPTION:Workshop\n\nMultilevel Simulation-Based Co-Design of Next Gene
 ration HPC Microprocessors\n\nZaourar, Benazouz, Mouhagir, Jebali, Sassola
 s...\n\nThis paper demonstrates the combined use of three simulation tools
  in support of a full co-design methodology for an HPC-focused SoC. The si
 mulation tools make different trade-offs among simulation speed, accuracy 
 and model abstraction level, and are shown to be complementary to one anot
 her. We apply the MUSA trace-based simulator for the initial sizing of vec
 tor register length, SLC size and memory bandwidth. It has proven to be ve
 ry efficient at pruning the design space, as its models enable good enough
  accuracy without the need to resort to highly detailed simulations.\n\nTh
 en we apply gem5, a cycle-accurate microarchitecture simulator, for a more
  refined analysis of the performance potential of our reference SoC archit
 ecture, with models able to capture detailed hardware behavior at the cost
  of simulation speed. Furthermore, we study NoC topology and IP placements
  using both gem5 for representative small- to medium-scale configurations 
 and SESAM/VPSim, a transaction-level emulator for larger scale systems wit
 h good simulation speed and sufficient architectural details.\n\nOverall, 
 we consider several system design concerns, such as processor subsystem si
 zing and NoC settings. We apply the selected simulation tools, focusing on
  different levels of abstraction, to study several configurations with var
 ious design concerns, and evaluate them to guide architectural design and 
 optimization decisions. Performance analysis is conducted with a number of
  representative benchmarks. The obtained numerical results provide guidanc
 e and hints to designers regarding SVE register length, SLC sizing and mem
 ory bandwidth, as well as the best placement of memory controllers and NoC
  form factor. Thus, we provide critical insights for efficient design of f
 uture HPC microprocessors.\n\nTag: Online Only, Accelerator-based Architec
 tures, Applications, Computational Science, Emerging Technologies, Extreme
  Scale Computing, File Systems and I/O, Heterogeneous Systems, Parallel Pr
 ogramming Languages and Models, Performance, Scientific Computing, Softwar
 e Engineering\n\nRegistration Category: Workshop Reg Pass
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