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DTSTART:19700308T020000
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211207T055347Z
LOCATION:Online
DTSTART;TZID=America/Chicago:20211115T140000
DTEND;TZID=America/Chicago:20211115T142000
UID:submissions.supercomputing.org_SC21_sess422_ws_pmbss103@linklings.com
SUMMARY:Using the Semi-Stencil Algorithm to Accelerate High-Order Stencils
  on GPUs
DESCRIPTION:Workshop\n\nUsing the Semi-Stencil Algorithm to Accelerate Hig
 h-Order Stencils on GPUs\n\nSai, Mellor-Crummey, Meng, Araya-Polo, Meng\n\
 nUnderstanding how to develop efficient high-order stencils for graphics p
 rocessing units (GPUs) is a topic of great interest for many application d
 omains. High-performance stencils on GPUs must be tailored for data parall
 el computation and to use the memory hierarchy efficiently. For data-inten
 sive high-order stencils, the key to high performance on GPUs is reducing 
 the shared memory footprint to enable a large thread block for hiding memo
 ry latency. In this paper, we use the semi-stencil algorithm to do so. On 
 the NVIDIA A100, a CUDA implementation of the semi-stencil algorithm along
  with other optimizations achieves a 2.13x speedup compared to an OpenACC 
 reference implementation and is 8.7% faster than the best conventional ste
 ncil computing out of shared memory. We evaluate the performance of our im
 plementations and their variants on the latest NVIDIA GPUs.\n\nTag: Online
  Only, Accelerator-based Architectures, Applications, Computational Scienc
 e, Emerging Technologies, Extreme Scale Computing, File Systems and I/O, H
 eterogeneous Systems, Parallel Programming Languages and Models, Performan
 ce, Scientific Computing, Software Engineering\n\nRegistration Category: W
 orkshop Reg Pass
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