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TZOFFSETTO:-0500
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DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
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DTSTART:19701101T020000
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BEGIN:VEVENT
DTSTAMP:20211207T055408Z
LOCATION:Online
DTSTART;TZID=America/Chicago:20211114T140000
DTEND;TZID=America/Chicago:20211114T150000
UID:submissions.supercomputing.org_SC21_sess426_misc346@linklings.com
SUMMARY:MCHPC’21 Afternoon Invited Talk:  New Trends for sPIN-Based In-Net
 work Computing – from Sparse Reductions to RISC-V Acceleration
DESCRIPTION:Workshop\n\nMCHPC’21 Afternoon Invited Talk:  New Trends for s
 PIN-Based In-Network Computing – from Sparse Reductions to RISC-V Accelera
 tion\n\nHoefler\n\nAccelerated in-network computations promise significant
  optimizations ranging from data-movement reductions to specialization opp
 ortunities in processing elements. We show updates within the sPIN (stream
 ing Processing in the Network) network accelerator programming model - the
  "CUDA for networking". There, we demonstrate 2x lower required bandwidth 
 for (sparse) reductions and a highly-optimized packet processing design ba
 sed on a low-power RISC-V multi-core architecture.\n\nTag: Online Only, Ar
 chitectures, Memory Systems, Parallel Programming Languages and Models, Sy
 stem Software and Runtime Systems\n\nRegistration Category: Workshop Reg P
 ass
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