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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211207T055408Z
LOCATION:Online
DTSTART;TZID=America/Chicago:20211114T160000
DTEND;TZID=America/Chicago:20211114T163000
UID:submissions.supercomputing.org_SC21_sess426_ws_mchpc101@linklings.com
SUMMARY:Memory Optimizations for Sparse Linear Algebra on GPU Hardware
DESCRIPTION:Workshop\n\nMemory Optimizations for Sparse Linear Algebra on 
 GPU Hardware\n\nWalden, Zubair, Stone, Nielsen\n\nAn effort to maximize me
 mory bandwidth utilization\nfor a sparse linear algebra kernel executing o
 n NVIDIA\nTesla V100 and A100 Graphics Processing Units (GPUs) is\ndescrib
 ed. The kernel consists of a block-sparse matrix-vector\nproduct and a ser
 ies of forward/backward triangular solves. The\ncomputation is memory-boun
 d and exhibits low arithmetic intensity.\nAn earlier implementation yield\
 ngood memory performance on the V100 architecture. However, a\nnew approac
 h, which assigns a warp to six rows of the matrix, is\nproposed for the A1
 00. In addition, two new features offered by\nthe A100 architecture are ex
 plored. L2 residency control enables\na portion of the L2 cache to be used
  for persistent data access,\nand the asynchronous copy instruction allows
  data to be loaded\ndirectly from the main memory into shared memory. The 
 new implementation improves memory bandwidth utilization from 71.5% to 81.
 2% of the peak available on the A100 architecture.\n\nTag: Online Only, Ar
 chitectures, Memory Systems, Parallel Programming Languages and Models, Sy
 stem Software and Runtime Systems\n\nRegistration Category: Workshop Reg P
 ass
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