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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211207T055411Z
LOCATION:229
DTSTART;TZID=America/Chicago:20211119T112300
DTEND;TZID=America/Chicago:20211119T112600
UID:submissions.supercomputing.org_SC21_sess504_ws_rsdha102@linklings.com
SUMMARY:Comparing LLC-Memory Traffic between CPU and GPU Architectures
DESCRIPTION:Workshop\n\nComparing LLC-Memory Traffic between CPU and GPU A
 rchitectures\n\nMonil, Lee, Vetter, Malony\n\nThe cache hierarchy in moder
 n CPUs and GPUs is becoming complex. The introduction of additional comple
 xities by manufacturers makes understanding the handshake between the memo
 ry access pattern and the cache hierarchy difficult. Moreover, the details
  of different cache policies are not publicly available. Therefore, the re
 search community relies on observation to understand the relation between 
 memory access patterns and cache hierarchy. Our previous studies delved in
 to different micro-architectures of Intel CPUs. In this study, GPUs from N
 VIDIA and AMD are taken into consideration. Even though the execution mode
 ls in CPUs and GPUs are distinct, this study attempts to correlate the beh
 avior of the cache hierarchy of CPUs and GPUs. Using the knowledge gathere
 d from Intel CPUs, the similarities and dissimilarities between CPUs and G
 PUs are identified. Through model evaluation, this study provides a proof 
 of concept that LLC-memory traffic can be predicted for sequential streami
 ng and strided access patterns on GPUs.\n\nTag: Architectures, Extreme Sca
 le Computing, Heterogeneous Systems\n\nRegistration Category: Workshop Reg
  Pass
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